[GUIDE] Legacy AMIBIOS8 make all compiled Settings available

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#1 | [GUIDE] Legacy AMIBIOS8 make all compiled Settings available datum

Mon May 24, 2021 11:04 pm (Last edited: Sat May 29, 2021 5:28 pm)

eierhals

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Posts:	16
Registered since:	04.10.2020
Location:	dev.root

Hi everyone,

after month of Try and Error, and using the Internet Archive to build up a big library with AMD tech files and Guides from the New Rebel Heaven Forums I finally finished my guide which basically consists of 2 parts.
The first part is rewritten from the new rebels heaven forum the credits goes to that users.
The second part is a modified easier method to find all the settings which are saved to CMOS/NVRAM on a running machine do some calculation and replace the one you need or want to unlock with settings which are useless or you do not need.
All the work is based on a 2048kb AMIBIOS8 files. It should work with smaller 1024kb ROM files or larger 4096kb. The method is the same.
As I write in the guide for Case #2 I think there is a tool which can also extract the CMOS Tokens from an Offline Image but I couldn't remember it's name or how I make it work. I really hope someone can give a hint.

I know this guide are late and we all need it years ago but for retro use and fun it is useful.
I can't give a download link to the needed tools maybe most of you already got them I dunno.

Find out the guide as attachment I also uploaded it to github: Obsole BIOS Guide PDF Document

Edit #1: Added 2 screenshots of the working system + a list of 41-Bytecodes which i calculated explicit for H8DGI-F

41070E - UnitID Clumping
410C16 - GFX Card Workaround
411816 - MCU FW for erratum77
411914 - AddOn ROM Display Mode
412416 - Hide Unused PCIE P2P Bridges
412418 - OnChip SATA Channel
412710 - SET - Core Configuration GPP1 P0/1
412714 - Bootup Num-Lock
413018 - SATA IDE Combined Mode
413510 - SET - Core Configuration GPP2 P0/1
413514 - Wait For 'F1' If Error
414310 - Peer-to-Peer among GPP1/GPP2
414314 - Hit 'DEL' Message Display
414511 - HT Extended Address
41480E - PCIe = Maximum Payload Size
41491A - Load onboard SAS Option Rom
414D18 - Flash Controller
415311 - HT Link Tristate
415618 - SureBoot Feature
41591A - PS2 KB/MS Wakeup
41600E - PCIe = Maximum Read Request Size
416311 - IOC Peer-to-Peer Mode
417811 - SATA PHY WORKAROUND
417c18 - AMI OEMB table
417F1A - Retry Boot Devices
418111 - C States Support
418712 - USB Mass Storage Reset Delay
418D18 - Headless Mode
419214 - GART Error Reporting
41AC12 - Display Mode
41B411 - Relaxed Ordering
41B419 - Watch Dog function
41C219 - Raid CodeBase
41C411 - Extended Tag Field
41c518 - PEF SUPPORT
41D411 - No Snoop
41DD0D - NB Deempasies Level
41E411 - Extended Synch
41EF18 - MPS Revision
41F50D - HT3 Link Power State
41731A - Power Button Function
419C12 - Restore on AC Power Loss
415407 - Default Boot Order
41651A - Resume On RTC Alarm
414907 - RTC Alarm Date (Days)
418110 - NB-SB Link ASPM
413216 - NP NB-SB VC1 Traffic Support
41DF1A - SPD Software Write-Protect
41F40F - Power Down Enable
410410 - Power Down Mode
41991A - SMCCMOS Tool Support
41A71A - Auto Load Default from Optimal
410C15 - CS Sparing Enable
418119 - OnBoard Marvell NIC
418D19 - Marvell NIC OPTROM
41B20A - OnBoard PCI IDE Controller
413E18 - PATA Channel Config
41C417 - OHCI HC(Bus 0 Dev 18 Fn 0)
41D017 - OHCI HC(Bus 0 Dev 18 Fn 1)
41DF17 - EHCI HC(Bus 0 Dev 18 Fn 2)
41EE17 - OHCI HC(Bus 0 Dev 19 Fn 0)
41FA17 - OHCI HC(Bus 0 Dev 19 Fn 1)
410918 - EHCI HC(Bus 0 Dev 19 Fn 2)
411818 - OHCI HC(Bus 0 Dev 20 Fn 5)
413415 - Powerdown Unused lanes
414015 - Powerdown Unused lanes
414C15 - Powerdown Unused lanes
415815 - Powerdown Unused lanes
416415 - Turn Off PLL During L1/L23
417015 - Turn Off PLL During L1/L23
417C15 - Turn Off PLL During L1/L23
418815 - Turn Off PLL During L1/L23
414019 - USB 2.0 Controller Mode
415119 - BIOS EHCI Hand-Off
416219 - Legacy USB1.1 HC Support
419C19 - Northbridge interrupt pin
41190E - OnChip SATA Type
41240B - IDE Detect Time Out (Sec)
417712 - Legacy USB Support
413B09 - Remap Port Device Number
415F09 - Remap Port Device Number
418309 - Remap Port Device Number
41A709 - Remap Port Device Number
41CB09 - Remap Port Device Number
41EF09 - Remap Port Device Number
41130A - Remap Port Device Number
41370A - Remap Port Device Number
415B0A - Remap Port Device Number
417F0A - Remap Port Device Number
419110 - Gen2 High Speed Mode
41A310 - Gen2 High Speed Mode
41B510 - Gen2 High Speed Mode
41C710 - Gen2 High Speed Mode
41D910 - Gen2 High Speed Mode
41EB10 - Gen2 High Speed Mode
41FD10 - Gen2 High Speed Mode
410F11 - Gen2 High Speed Mode
412111 - Gen2 High Speed Mode
413311 - Gen2 High Speed Mode
413617 - Compliance Mode
414217 - Compliance Mode
414E17 - Compliance Mode
415A17 - Compliance Mode
416617 - Compliance Mode
417217 - Compliance Mode
417E17 - Compliance Mode
418A17 - Compliance Mode
419617 - Compliance Mode
41A217 - Compliance Mode
41AE17 - Compliance Mode
41C30C - Link Width
41D90C - Link Width
41EF0C - Link Width
415110 - Link Width
416110 - Link Width
417110 - Link Width
41D013 - Clear NVRAM
41510C - Core Configuration
41C70F - Reserved Memory Size
41EC13 - PCI IDE BusMaster
41690C - TX Drive Strength
417B0C - TX Drive Strength
418D0C - TX Drive Strength
419F0C - TX Drive Strength
41B10C - TX Drive Strength
419415 - TXCLK Clock Gating in L1
41A015 - TXCLK Clock Gating in L1
41AC15 - TXCLK Clock Gating in L1
41B815 - TXCLK Clock Gating in L1
41C415 - TXCLK Clock Gating in L1
41D015 - LCLK Clock Gating in L1
41DC15 - LCLK Clock Gating in L1
41E815 - LCLK Clock Gating in L1
41F415 - LCLK Clock Gating in L1
410016 - LCLK Clock Gating in L1
414C16 - Lane Reversal
415816 - Lane Reversal
416416 - Lane Reversal
417016 - Lane Reversal
417C16 - Lane Reversal
418816 - Lane Reversal
419416 - Lane Reversal
41FD18 - Active State Power Management
41AB11 - BMC Watch Dog Timer Action
41110C - Memory Timing Parameters
41340C - Memory Clock Speed
41AA18 - SR-IOV Supported
41B618 - ARI Forwarding
410814 - Quiet Boot

I will help as much as I can and feel free to ask for question.
P.s.: If anyone has a better Thread headline I am open to it

1
 
I do not accept any guarantee or responsibility in the event of incorrect application or use of these instructions. The risk is borne by each individual

Alex

eierhals has attached files to this post

Obsolete_BIOS_Guide.pdf

eierhals has attached images to this post

02-01.jpg

doc_2021-05-19_20-05-43.j

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