@DarkPoe: Depending on the mainboard manufacturer it becomes more and more difficult to get a modded BIOS flashed the easy way.
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chipsec has finally merged @kerneis-anssi's amd updates.
So now you can run the following:
1
$ sudo python3 chipsec_util.py reg read SPICntrl0
Which will output something like the following:
1 2 3 4 5 6 7 8 9 10 11
[CHIPSEC] SPICntrl0=0x4F0C2105 [*] SPICntrl0 = 0x4F0C2105 << SPI_Cntrl0. Reset: 0FC0_0000h. [18] SpiReadMode[0] = 1 << Read-write. Reset: 0. Bit[0] of SpiReadMode. See the definition of SpiReadMode[2:1] in this register. SpiReadMode = {SpiReadMode[2:1],SpiReadMode[0]}. [21] IllegalAccess = 0 << Read-only. Reset: 0. 0=Legal index mode access. 1=Illegal index mode access. [22] SpiAccessRomEn = 0 << Read,Write-0-only. Reset: 1. 0=Software cannot access MAC's portion of the ROM space (lower 512 KB). 1=Software can access MAC's portion of the ROM space. This is a clear-once protection bit. Once set, some SPI registers can't be written and discards a SPI request if it is an illegal request. [23] SpiHostAccessRomEn = 0 << Read,Write-0-only. Reset: 1. 0=MAC cannot access BIOS ROM space (upper 512 KB). 1=MAC can access BIOS ROM space. This is a clear-once protection bit. Once set, some SPI registers can't be written and discards a SPI request if it is an illegal request. [24] ArbWaitCount = 7 << Read-write. Reset: 7h. Specifies the amount of wait time the SPI controller asserts HOLD# before it should access the SPI ROM, under ROM sharing mode with the MAC. This time is to allow the MAC to sample HOLD#. [27] SpiBridgeDisable = 1 << Read-write. Reset: 1. Setting this bit disables the SPI bridge mode (SB acts as a SPI-LPC bridge to the MAC). [28] SpiClkGate = 0 << Read-write. Reset: 0. 1=Skip the 8th SPI clock at the end data when doing read. [29] SpiReadMode[2:1] = 2 << Read-write. Reset: 0h. Description: See Table 78 [SpiReadMode[2:0]]. NOTE: SPI modes supported are listed below, [31] SpiBusy = 0 << Read-only. Reset: 0. 0=SPI bus is idle. 1=SPI bus is busy.
Now you can clearly see that SpiAccessRomEn and SpiHostAccessRomEn and both set to 0. This means the BIOS ROM space is protected.
@DarkPoe the only way around this would be to remove the appropriate modules from the BIOS before upgrading to one that unsets these bits. As mentioned in my previous post.
I have yet to hear if anyone has done this successfully.
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Mon Oct 11, 2021 9:09 pm
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