I've managed to get my hands on a 2xXeon-2670 v1, 64GB vram server board (with CPUs and memory).

Turns out, they've put non QVL U-DIMMS on the board, and the MRC boots both cpus in single-channel mode. Those dimms (marked as HX318C9SRK2_16 on a sticker) are correctly placed, their JEDEC profile (1600 CL11) matches but everything looks like it's working in single channel. (they support XMP profiles for 1866, CPU does not support it) QVL dimms are hard to find, end-of life, expensive, and I was hoping avoid buying new ones or shelving the board. Contacting the manufacturer, got the classic response, out of luck buddy, need QVL mems.

Digging through the BIOS, I've managed to un-hide "Serial Message Debug Level" option which can be set to "Trace", and I was hoping to be able to get the MRC to trace its boot, and then find out where the thing goes wrong. Searching through the internet confirmed that it's related to Memory Training, as other boards had a one-liner documenting this setting, and poking through the MRC binary (5C08C7C8-24C2-4400-9627-CF2869421E06_IvtQpiandMrcInit) seems to be indeed used for logging.

Does anyone have experience with that setting and how to get these logs out?

I was also able to find a one byte '97CA1A5B-B760-4D1F-A54B-D19092032C90:DebuggerSerialPortsEnabledVar' from the nvram, it's referenced by DXEs only, and I'm interested in the early PEIM memory start-up, so I'm not sure if I should poke at it.

I've also looked through the MrcNVramData, and the interesting thing there is that the memory modules are marked as KHX1866C9D3/8GX (which looks like the Single rank version of the installed DIMMs). No luck yet with the SPD info, as linux's dmidecode doesn't work well with this board (2 cpus I guess)

Thanks!

Edit: added thanks :)