Forum - RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization

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#406 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Sat Jul 24, 2021 4:15 pm (Last edited: Sat Jul 24, 2021 11:50 pm)

I'm trying to clean my ME region, and I have a couple of questions, please...
1) the outimage.bin results in Extracted and not Region, is this correct?
2) as the ME region extracted from the CAP file is already Configured, I could flash just that one to have a cleaned region, right?

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#407 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Wed Aug 11, 2021 9:46 pm

@ plutomaniac
when try to clean me of old version 6 showing wrong sku selection.
even i use same me reposiatory or simply build image without change me its showing same error.
uploading my working backup with reposiatory
please check.
thankyou

earthoo7 has attached files to this post

backup.rar

earthoo7 has attached images to this post

sku error.jpg

supported versions.jpg

using same me.jpg

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#408 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Mon Aug 23, 2021 11:23 am

Hello sir, I have a question for you. I've tried your tutorial. But it was still no display on my laptop. I have tried to replace ME Region so many time. And the result was still same. But when I replace file BIOS Region. It work. So this is my question. What is the different between ME Region and BIOS Region sir?

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#409 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Mon Oct 11, 2021 2:56 pm

FIT 12 and 14 refuse to work on a ME region extracted with UEFIToolNE.

Tried extracted ME region from Dell 7080 MFF Enable Intel AMT and out of curiousity extracted ME Regions from a Q370 dump (M920q- ME12) and the stock bios of an Asus Q470 board (link)

Either it's "Error 237: Failed to load input file. Invalid input file type." or "Error 9: Failed to decompose Image." (when removing padding over a certain point).

From the extracted complete bios the ME Sub Partition.bin can be opened in FIT, but it seems to be a constructed file, not part of the original CSE Region. The extracted CSE region.bin is identical to a otherwise extracted ME Region and can't be opened in FIT.

How can one work on a ME region for ME12 and ME 14? Did I miss something?

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#410 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Mon Oct 11, 2021 3:12 pm

Zitat von lfb6 im Beitrag #409
FIT 12 and 14 refuse to work on a ME region extracted with UEFIToolNE.

That's normal/expected, as explained here. For CSME >= 12, you need to work on the entire SPI image.

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#411 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Mon Oct 11, 2021 5:16 pm (Last edited: Mon Oct 11, 2021 5:58 pm)

Thanks! But the thread you mentioned was regarding updating ME, not cleaning, and that part is fully understandable.

But regarding 'getting the configuration' for cleaning I can't see the difference in opening a complete ME14- firmware image and a ME14 CSME region compared to ME 11?

OK it might be information added or moved into FD, or- since there were settings stored in FD ealrier, too- they changed the standard behaviour from "assuming default values" to "rejecting the CSME region without information stored in FD"

So for working on a CSME region => ME12 only for cleaning one could use:

- An extracted CSME region and the dumped FD, filling the rest of the firmware with FF, keeping starting addresses or

- An extracted CSME region and any FD fitting for the chipset, filling the rest of the firmware with FF, keeping starting addresses. Settings in FD wouldn't get touched when flashing back just the cleaned ME so those settings wouldn't matter or

- An extracted CSME region and any FD fitting containing the right addresses, everything else after 0x7F being FFed (see spoiler), filling the rest of the firmware with FF, keeping starting addresses. Settings in FD wouldn't get touched when flashing back just the cleaned ME, so those settings wouldn't matter.

Warning: Could not set "GPPC_G Group Master Voltage Select" to: 0x000000FF, reverting to previous/default value: 3.3Volts
Warning: Could not set "USB3 Port 8 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 7 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 6 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type C
Warning: Could not set "USB3 Port 5 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 4 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 3 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 2 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 1 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 6 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 5 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 4 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 3 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 2 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 1 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB3 Port 10 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Express Card / M.2 S2
Warning: Could not set "USB3 Port 9 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Express Card / M.2 S2
Warning: Could not set "USB2 Port 14 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Express Card / M.2 S2
Warning: Could not set "USB2 Port 13 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 12 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 11 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 10 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 9 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type C
Warning: Could not set "USB2 Port 8 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type A
Warning: Could not set "USB2 Port 7 Connector Type Select" to: 0x0000000F, reverting to previous/default value: Type C
Warning: Could not set "Top Swap Block Size" to: 0x00000007, reverting to previous/default value: 128KB
Warning: Could not set "Intel(R) Precise Touch and Stylus Controller 2 Maximum Frequency" to: 0x00000007, reverting to previous/default value: 24 MHz
Warning: Could not set "TPM Clock Frequency" to: 0x00000007, reverting to previous/default value: 17MHz
Warning: Could not set "Intel(R) Precise Touch and Stylus Controller 1 Maximum Frequency" to: 0x00000007, reverting to previous/default value: 30 MHz
Warning: Could not set "eSPI / EC Slave Device Bus Frequency" to: 0x00000007, reverting to previous/default value: 60MHz
Warning: Could not set "DMI Lane Width" to: 0x00000007, reverting to previous/default value: DMI x4
Warning: Could not set "Intel(R) RST for PCIe-C3 Select x2 or x4" to: 0x00000003, reverting to previous/default value: x4
Warning: Could not set "Intel(R) RST for PCIe-C2 Select x2 or x4" to: 0x00000003, reverting to previous/default value: x4
Warning: Could not set "Intel(R) RST for PCIe-C1 Select x2 or x4" to: 0x00000003, reverting to previous/default value: x4
Warning: Could not set "GbE \ PCIe Port Select 5" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 5" to: 0x0000000F, reverting to previous/default value: SATA
Warning: Could not set "SATA / PCIe Combo Port 4" to: 0x0000000F, reverting to previous/default value: SATA
Warning: Could not set "SATA / PCIe Combo Port 3" to: 0x0000000F, reverting to previous/default value: SATA
Warning: Could not set "SATA / PCIe Combo Port 2" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 1" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 0" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "GbE \ PCIe Port Select 9" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 9" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 8" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 7" to: 0x0000000F, reverting to previous/default value: PCIe
Warning: Could not set "SATA / PCIe Combo Port 6" to: 0x0000000F, reverting to previous/default value: GPIO Polarity PCIe
Warning: Could not set "PHY Connection" to: 0x00000007, reverting to previous/default value: PHY on SMLink0
Warning: Could not set "Number of Active Cores" to: 0x0000000F, reverting to previous/default value: All Cores Active
Warning: Could not set "Number of Active Cores" to: 0x0000000F, reverting to previous/default value: All Cores Active
Warning: Could not set "Intel(R) ME Boot Stall Enabled" to: 0x000000FF, reverting to previous/default value: No Boot Stall

[Edit]It seems that in most cases one needs a complete/ valid FD for opening the ME region in Fit for cleaning. Taking an FD from a board with same ME / chipset seems to work after adapting the addresses.

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#412 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Tue Oct 12, 2021 12:27 pm

Flash Image Tool (FIT) accepts Engine firmware images in Flash Partition Table ($FPT) format only, which is how the firmware are structured initially and how they were stored in the Engine region of the SPI/BIOS chip up until CSME 11. Starting from CSME 12, the initial $FPT formatted firmware is inputted into FIT, configured and then stored in CSE Layout Table (LT) format in the Engine region of the SPI/BIOS chip, not $FPT. Bottom line is this: you cannot use an (e.g. UEFITool) extracted "Engine" (CSE LT) SPI/BIOS chip region image at FIT for cleaning anymore. You'll need to have and load the full SPI/BIOS image (FD+CSME+BIOS).

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#413 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

Wed Nov 10, 2021 11:20 am (Last edited: Wed Nov 10, 2021 11:50 am)

As I could not find anyone confirming they had done it I will report here.

I successfully upgraded my ASRock J4205-ITX that is Apollo Lake Goldmont atom SoC.
ASRock is using full bios update images so there is no need for SPI dump, but just to be safe I used an external programmer to dump the unmodified bios for backup. But it was not needed.

This SoC is still actively supported by Intel in their NUC6 series low power computers. I used MEAnalyzer and saw that although the NUC6 series is running the latest TXE it is not using the latest APL Power Management Controller firmware. Even more interesting is that Intel has quietly moved to newer PMC firmwares over the years on the NUC6 even though they publish quite a detailed bios change log. The most recent 3.1.x TXE that is "clean" is 3.1.75.2351_B_PRD_RGN.bin, so a bit older than NUC6 3.1.86.2538. And just as a precaution 3.1.75 is the last TXE 3 on ARB version 3:
TXE version ARB VCN
3.1.75.2351 3 69
3.1.80.2400 4 71
3.1.86.2538 5 82
Some documentation suggests that once ARB version number is updated in the chip it is impossible to revert to previous version even if you have a valid SPI image dump.

So that is why I chose APL_0.1.0.0_B_2019-02-04_PRD.bin for the PMC to match latest NUC6 bios and 3.1.75.2351_B_PRD_RGN.bin for TXE. And of course the latest microcode can be used when creating this new bios image. Although for a simple microcode update operation the complex FIT process is not needed, one can use a hex editor replacing the included microcode with a new one and no other checksum etc fixing is needed for this bios image. ASRock uses no verification on this bios so flashing the modified image from the bios setup was straightforward.

In the end the versions updated:
TXE 3.1.50.2222 > 3.1.75.2351
PMC 2016-08-10 > 2019-02-04
MC 2E > 46

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#414 | RE: [Guide] Clean Dumped Intel Engine (CS)ME/(CS)TXE Regions with Data Initialization datum

4 minutes ago

Zitat von Marvin im Beitrag #413
Some documentation suggests that once ARB version number is updated in the chip it is impossible to revert to previous version even if you have a valid SPI image dump.

True, but it started to apply from CSME 12 and newer firmware. It was optional at first but became obligatory afterwards (CSME 13 maybe, don't remember). For CSME 11 and CSTXE 3-4, neither TCB nor ARB SVN are enforced through the HW/Chipset/Fuses so you can go back to older values with external means (programmer etc).

Zitat von Marvin im Beitrag #413
Although for a simple microcode update operation the complex FIT process is not needed, one can use a hex editor replacing the included microcode with a new one and no other checksum etc fixing is needed for this bios image.

CSTXE 3-4 use IFWI 2.0 which includes the microcodes within a $CPD partition, just like CSTXE code & date. The $CPD header does have a Checksum-8, but it covers the offset & sizes only, not the data (microcode) afterwards. However, if the new microcode is smaller or larger, the equivalent $CPD Entry fields will need to be adjusted, which will require calculating the Checksum-8 again. I assume it worked in your case because the new microcode was of the exact same size, but it's not always like that. You can check these things via MEA unpacking (-unp86 -bug86) for CSTXE.

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Any way to unhide the heci/mei device with coreboot? I need this device to exist for hd4000 acceleration to work on osx. Its related to rcba settings?? Thx �

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